The technology scaling of the integrated circuit is driving down the size of capacitor trench in a memory cell. Generally, the size scaling of capacitor trench may reduce the contact area between a capacitor dielectric layer and an electrode, and therefore the capacitance value may also be reduced. Therefore, a capacitor trench 800 as shown in FIG. 8 has been developed. This structure can increase the contact area between the capacitor dielectric layer and the electrode without affecting the size of the capacitor trench.
However, the well-known method of manufacturing the capacitor trench 800 involves multiple steps. For example, in the well-known process, a trench 802 is formed in the silicon substrate 801 first, and then a conformal sacrificial layer is formed to cover an inner wall and a bottom surface of the trench 802. Next, a part of the conformal sacrificial layer located on the bottom surface of the trench 802 is removed to form a collar sacrificial layer. A polysilicon layer 803 is deposited in the trench, and then etched back to a predetermined depth. Finally, the collar sacrificial layer is removed by a selective etching process to form the structure shown in FIG. 8. Because the above-mentioned conventional method is so complicated and time-consuming, it is necessary to provide an efficient method to overcome these problems of the prior art.